Early-Stage Neural Network Hardware Performance Analysis

Convolutional Neural Networks (CNNs) have become common in many fields including computer vision, speech recognition, and natural language processing. Although CNN hardware accelerators are already included as part of SoC architectures, the task achieving high accuracy on resource-restricted devices is still considered challenging, mainly due to vast number design parameters that need be balanced achieve an efficient solution. Quantization techniques, when applied network parameters, lead a reduction power area may also change ratio between communication computation. As result, some algorithmic solutions suffer from lack memory bandwidth or computational resources fail expected performance constraints. Thus, system designer micro-architect understand at early development stages impact their high-level decisions (e.g., architecture amount bits used represent its parameters) final product saving, area, accuracy). Unfortunately, existing tools fall short supporting such decisions. This paper introduces hardware-aware complexity metric aims assist neural through entire project lifetime (especially stages) by predicting architectural micro-architectural product. We demonstrate how proposed can help evaluate different alternatives models real-time embedded systems, avoid making mistakes stages.